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general description the MAX8764 pulse-width modulation (pwm) controller provides high efficiency, excellent transient response, and high-dc output accuracy needed for stepping down high-voltage batteries to generate low-voltage cpu core or chipset/ram supplies in notebook com- puters. maxim? proprietary quick-pwm quick-response, constant-on-time pwm control scheme handles wide input/output voltage ratios with ease and provides 100ns ?nstant-on?response to load transients while maintaining a relatively constant switching frequency. efficiency is enhanced by an ability to drive very large synchronous-rectifier mosfets. accurate current sens- ing to ensure reliable overload protection is available using an external current-sense resistor in series with the synchronous rectifier. alternatively, the synchronous rectifier itself can be used for less-accurate current sensing at the lowest possible power dissipation. a high-output impedance in shutdown eliminates nega- tive output voltages, saving the cost of a schottky diode on the output. single-stage buck conversion allows the MAX8764 to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down the 5v system supply instead of the battery) at a higher switching frequency allows the mini- mum possible physical size. the MAX8764 is intended for cpu core, chipset, dram, or other low-voltage supplies as low as 1v. it is available in 20-pin qsop and thin qfn packages and includes both adjustable overvoltage and undervoltage protection. for a dual step-down pwm controller with accurate cur- rent limit, refer to the max8743 data sheet. the max1714/max1715 single/dual pwm controllers are similar to the MAX8764, but do not use current-sense resistors. applications notebook computers cpu core supplies chipset/ram supplies as low as 1v 1.8v and 2.5v supplies features ? ultrahigh efficiency ? accurate current-limit option ? quick-pwm with 100ns load-step response ? 1% v out accuracy over line and load ? 1.8v/2.5v fixed or 1v to 5.5v adjustable output range ? 2v to 28v battery input range ? 200/300/450/600khz switching frequency ? adjustable overvoltage protection ? adjustable undervoltage protection ? 1.7ms digital soft-start ? drives large synchronous-rectifier fets ? 2v 1% reference output ? power-good window comparator MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ________________________________________________________________ maxim integrated products 1 19-3626; rev 0; 3/05 pin configurations appear at end of data sheet. quick-pwm is a trademark of maxim integrated products, inc. v cc 5v input battery 4.5v to 28v output 2.5v shdn ilim dl lx v+ bst dh cs out skip v dd MAX8764 uvp ref pgood latch ovp fb gnd minimal operating circuit for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package MAX8764eep -40c to +85c 20 qsop MAX8764eep+ -40c to +85c 20 qsop MAX8764etp -40c to +85c 20 thin qfn MAX8764etp+ -40c to +85c 20 thin qfn + denotes lead-free package.
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +28v v cc , v dd to gnd .....................................................-0.3v to +6v out, pgood, shdn to gnd ..................................-0.3v to +6v fb, ilim, latch , ovp, ref, skip , ton, uvp to gnd ..................................-0.3v to (v cc + 0.3v) bst to gnd ............................................................-0.3v to +34v cs to gnd.................................................................-6v to +30v dl to gnd ..................................................-0.3v to (v dd + 0.3v) dh to lx .....................................................-0.3v to (bst + 0.3v) lx to bst..................................................................-6v to +0.3v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70?) 20-pin qsop (derate 9.1mw/ c above +70 c)...........727mw 20-pin 5mm x 5mm thin qfn (derate 20.0mw/? above +70?).................................................................1.60w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, skip = latch = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v fb = out 0.99 1.01 fb = gnd 2.475 2.5 2.525 error comparator threshold (dc output voltage accuracy) (note 1) v+ = 4.5v to 28v, skip = v cc fb = v cc 1.782 1.8 1.818 v load regulation error i load = 0 to 3a, skip = v cc 9 mv line regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v 5 mv fb input bias current -0.1 +0.1 ? output adjustment range 1.0 5.5 v fb = gnd 90 190 350 out input resistance fb = v cc or adjustable feedback mode 70 145 270 k ? soft-start ramp time rising edge of shdn to full current limit 1.7 ms ton = gnd (600khz) 140 160 180 ton = ref (450khz) 175 200 225 ton = unconnected (300khz) 260 290 320 on-time v+ = 24v, v out = 2v (note 2) ton = v cc (200khz) 380 425 470 ns minimum off-time (note 2) 400 500 ns quiescent supply current (v cc ) fb forced above the regulation point 550 800 ? quiescent supply current (v dd ) fb forced above the regulation point <1 5 ? quiescent supply current (v+) 25 40 ? shutdown supply current (v cc ) shdn = gnd <1 5 ? shutdown supply current (v dd ) shdn = gnd <1 5 ? shutdown supply current (v+) shdn = gnd, v+ = 28v, v cc = v dd = 0 or 5v <1 5 ? reference voltage v cc = 4.5v to 5.5v, no external ref load 1.98 2.00 2.02 v reference load regulation i ref = 0 to 50? 0.01 v
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, skip = latch = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units ref sink current ref in regulation 10 ? ref fault lockout voltage falling edge, hysteresis = 40mv 1.6 v overvoltage trip threshold (fixed-threshold mode) with respect to error comparator threshold, no load ovp = gnd, rising edge, hysteresis = 1% 12 14.5 17 % external feedback, measured at fb with respect to v ovp , 1v < v ovp < 1.8v, rising edge, hysteresis =1% -30 +30 mv overvoltage comparator offset (adjustable-threshold mode) internal feedback, measured at out with respect to the nominal out regulation voltage, 1v < v ovp < 1.8v, rising edge, hysteresis = 1% -3.5 +3.5 % ovp input leakage current 1v < v ovp < 1.8v -100 0 +100 na overvoltage fault propagation delay fb forced 2% above trip threshold 1.5 ? output undervoltage protection trip threshold (fixed-threshold mode) with respect to error comparator threshold, uvp = v cc 65 70 75 % external feedback, measured at fb with respect to v uvp , 0.4v < v uvp < 1v -40 +40 mv output undervoltage protection trip threshold (adjustable- threshold mode) internal feedback, measured at out with respect to the nominal out regulation voltage, 0.4v < v uvp < 1v -5 +5 % uvp input leakage current 0.4v < v uvp < 1v -100 <1 +100 na output undervoltage protection blanking time from rising edge of shdn 10 30 ms pgood trip threshold (lower) with respect to error comparator threshold, no load -12.5 -10 -8.0 % pgood trip threshold (upper) with respect to error comparator threshold, no load 8.0 10 12.5 % pgood propagation delay fb forced 2% beyond pgood trip threshold, falling 10 ? pgood output low voltage i sink = 1ma 0.4 v pgood leakage current high state, forced to 5.5v 1 ? ilim adjustment range 0.25 3.00 v current-limit threshold (fixed) gnd - v cs , ilim = v cc 90 100 110 mv v ilim = 0.5v 40 50 60 current-limit threshold (adjustable) gnd - v cs v ilim = 2v 170 200 230 mv current-limit threshold (negative direction) gnd - v cs , skip = v cc , ilim = v cc , t a = +25? -140 -117 -95 mv current-limit threshold (zero crossing) gnd - v cs, skip = gnd 3 mv thermal shutdown threshold hysteresis = 10? +150 ? v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, skip = latch = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units MAX8764eep 1.5 5 dh gate-driver on-resistance bst - lx forced to 5v (note 4) MAX8764etp 1.5 6 ? MAX8764eep 1.5 5 dl gate-driver on-resistance dl, high state (note 4) MAX8764etp 1.5 6 ? MAX8764eep 0.5 1.7 dl gate-driver on-resistance dl, low state (note 4) MAX8764etp 0.5 2.7 ? dh gate-driver source/sink current dh forced to 2.5v, bst-lx forced to 5v 1 a dl gate-driver source current dl forced to 2.5v 1 a dl gate-driver sink current dl forced to 5v 3 a dl rising 35 dead time dh rising 26 ns logic input high voltage latch , shdn , skip 2.4 v logic input low voltage latch , shdn , skip 0.8 v logic input current latch , shdn , skip -1 +1 ? dual mode threshold, low ovp, uvp, fb 0.15 0.20 0.25 v ovp, uvp v cc - 1.5 v cc - 0.4 dual mode threshold, high fb 1.9 2.0 2.1 v ton v cc level v cc - 0.4 v ton float voltage 3.15 3.85 v ton reference level 1.65 2.35 v ton gnd level 0.5 v ton input current forced to gnd or v cc -3 +3 ? ilim input leakage current -100 0 +100 na parameter conditions min typ max units battery voltage, v+ 2 28 input voltage range v cc , v dd 4.5 5.5 v fb = out 0.985 1.015 fb = gnd 2.462 2.538 error comparator threshold (dc output voltage accuracy) v+ = 4.5v to 28v, skip = v cc (note 1) fb = v cc 1.773 1.827 v ton = gnd (600khz) 140 180 ton = ref (450khz) 175 225 ton = unconnected (300khz) 260 320 on-time v+ = 24v, v out = 2v (note 2) ton = v cc (200khz) 380 470 ns electrical characteristics (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, skip = latch = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 3) dual mode is a trademark of maxim integrated products, inc.
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers _______________________________________________________________________________________ 5 parameter conditions min typ max units minimum off-time (note 2) 500 ns quiescent supply current (v cc ) fb forced above the regulation point 800 ? quiescent supply current (v dd ) fb forced above the regulation point 5 ? quiescent supply current (v+) measured at v+ 40 ? shutdown supply current (v cc ) shdn = gnd 5 ? shutdown supply current (v dd ) shdn = gnd 5 ? shutdown supply current (v+) shdn = gnd, v+ = 28v, v cc = v dd = 0 or 5v 5 ? reference voltage v cc = 4.5v to 5.5v, no external ref load 1.98 2.02 v overvoltage trip threshold (fixed-threshold mode) with respect to error comparator threshold, no load ovp = gnd, rising edge, hysteresis = 1% 12 17 % external feedback, measured at fb with respect to v ovp , 1v < v ovp 1.8v, rising edge, hysteresis = 1% -30 +30 mv overvoltage comparator offset (adjustable-threshold mode) internal feedback, measured at out with respect to the nominal out regulation voltage, 1v < v ovp < 1.8v -3.5 +3.5 % output undervoltage protection trip threshold (fixed threshold mode) with respect to error comparator threshold, uvp = v cc 65 70 75 % output undervoltage protection trip threshold (adjustable mode) measured at fb/out with respect to v uvp ; 0.4v < v uvp < 1.0v -5 +5 % pgood trip threshold (lower) with respect to error comparator threshold, no load out falling edge, hysteresis = 1% -12.5 -7.5 % pgood trip threshold (upper) with respect to error comparator threshold, no load out rising edge, hysteresis = 1% 7.5 12.5 % pgood output low voltage i sink = 1ma 0.4 v pgood leakage current high state, forced to 5.5v 1 ? current-limit threshold (fixed) gnd - v cs , ilim = v cc 85 115 mv gnd - v cs , v ilim = 0.5v 35 65 current-limit threshold (adjustable) gnd - v cs , v ilim = 2v 160 240 mv v cc undervoltage lockout threshold rising edge, hysteresis = 20mv, pwm disabled below this level 4.1 4.4 v logic input high voltage latch , shdn , skip 2.4 v logic input low voltage latch , shdn , skip 0.8 v logic input current latch , shdn , skip -1 +1 ? electrical characteristics (continued) (circuit of figure 1, v+ = 15v, v cc = v dd = 5v, skip = latch = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 3) note 1: when the inductor is in continuous conduction, the output voltage has a dc regulation level higher than the error compara- tor threshold by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regu- lation level higher than the trip level by approximately 1.5% due to slope compensation. note 2: on-time and off-time specifications are measured from 50% point to 50% point at the dh pin with lx = gnd, v bst = 5v, and a 250pf capacitor connected from dh to lx. actual in-circuit times may differ due to mosfet switching speeds. note 3: specifications to -40? are guaranteed by design, not production tested. note 4: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin qfn package. the MAX8764eep and MAX8764etp contain the same die and the thin qfn package imposes no additional resistance in-circuit.
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 6 _______________________________________________________________________________________ 100 60 0.01 1 10 efficiency vs. load current 70 65 75 80 85 90 95 MAX8764 toc01 load current (a) efficiency (%) 0.1 v in = 7v v in = 12v v in = 20v 350 0 0.01 1 10 frequency vs. load current 100 50 150 200 250 300 MAX8764 toc02 load current (a) frequency (khz) 0.1 v in = 15v, skip = v cc v in = 15v, skip = gnd v in = 7v, skip = gnd v in = 7v, skip = v cc 320 310 300 290 280 015 510 202530 frequency vs. input voltage MAX8764 toc03 input voltage (v) frequency (khz) i load = 1a 290 300 310 320 330 -40 -10 20 50 -25 5 35 65 80 frequency vs. temperature MAX8764 toc04 temperature ( c) frequency (khz) i load = 1a i load = 4a -40 5 20 -25 -10 35 50 65 80 current limit vs. temperature MAX8764 toc07 temperature ( c) current limit (a) 3 4 5 6 0 100 200 300 400 500 600 700 800 010 5 15202530 continuous-to-discontinuous inductor current vs. input voltage MAX8764 toc05 input voltage (v) load current (ma) continuous inductor current discontinuous inductor current 0 1 2 3 4 5 6 7 8 010 5 15202530 current limit vs. input voltage MAX8764 toc06 input voltage (v) current limit (a) 1.8 1.6 1.4 1.2 1.0 1.0 1.4 1.2 1.6 1.8 normalized overvoltage trip threshold vs. v ovp MAX8764 toc08 v ovp (v) normalized threshold (v/v) overvoltage trip threshold output voltage set point 110 112 116 114 118 120 -40 10 -15 35 60 85 overvoltage trip threshold vs. temperature MAX8764 toc09 temperature ( c) overvoltage trip threshold (%) __________________________________________typical operating characteristics (circuit of figure 1, v in = 15v, skip = latch = gnd, ton = unconnected, t a = +25?, unless otherwise noted.)
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers _______________________________________________________________________________________ 7 0 2 6 4 8 10 010 5 15202530 no-load supply current vs. input voltage (pwm mode) MAX8764 toc10 input voltage (v) supply current (ma) i in i dd i cc 0.8 0.6 0.4 0.2 0 015 510 202530 no-load supply current vs. input voltage (skip mode) MAX8764 toc11 input voltage (v) supply current (ma) i cc i in i dd 20 s/div load-transient response (pwm mode) inductor current 2a/div v out ac-coupled 100mv/div dl 5v/div MAX8764 toc12a 20 s/div load-transient response (skip mode) inductor current 2a/div v out ac-coupled 100mv/div dl 5v/div MAX8764 toc12b 400 s/div startup MAX8764 toc14 v out 2v/div shdn 5v/div pgood 5v/div dl 5v/div inductor current 5a/div r load = 0.4 ? 40 s/div output overload waveform (uvp = gnd) v out 2v/div load fet 2v/div pgood 5v/div dl 5v/div inductor current 5a/div MAX8764 toc13a 40 s/div output overload waveform (uvp = v cc ) MAX8764 toc13b v out 2v/div load fet 2v/div pgood 5v/div dl 5v/div inductor current 5a/div 100 s/div shutdown waveform MAX8764 toc15a r load = 0.4 ? v out 2v/div shdn 5v/div pgood 5v/div dl 5v/div inductor current 5a/div 1ms/div output overvoltage waveform (ovp = gnd) v out 1v/div pgood 5v/div dl 5v/div inductor current 5a/div MAX8764 toc15b typical operating characteristics (continued) (circuit of figure 1, v in = 15v, skip = latch = gnd, ton = unconnected, t a = +25?, unless otherwise noted.)
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 8 _______________________________________________________________________________________ pin qsop thin qfn name function 1 18 cs current-sense input. connect a low-value, current-sense resistor between cs and gnd for accurate current sensing. for lower power dissipation (less accurate) current sensing, connect cs to lx to use the synchronous rectifier as the sense resistor. the pwm controller does not begin a cycle unless the current sensed at cs is less than the current-limit threshold programmed at ilim. 2 19 latch overvoltage protection latch control input. the synchronous rectifier mosfet is always forced to the on state when an overvoltage fault is detected. if latch is low, the synchronous rectifier remains on until either ovp is brought high, or v cc is cycled below 1v. if latch is high, the fault protections (uvp and ovp) are disabled. 3 20 shdn shutdown control input. drive shdn to gnd to force the max1844 into shutdown. drive or connect to v cc for normal operation. a rising edge on shdn clears the overvoltage and undervoltage protection fault latches. 4 1 ovp overvoltage protection control input. an overvoltage fault occurs if the internal or external feedback voltage exceeds the voltage at ovp. apply a voltage between 1v and 1.8v to set the overvoltage limit between 100% and 180% of nominal output voltage. connect to gnd to assert the default overvoltage limit at 114% of the nominal output voltage. connect ovp or latch to v cc to disable overvoltage fault detection and clear the overvoltage protection fault latch. 5 2 fb feedback input. connect to v cc for a 1.8v fixed output or to gnd for a 2.5v fixed output. for an adjustable output (1v to 5.5v), connect fb to a resistive divider from the output voltage. the fb regulation level is 1v. 6 3 out output-voltage sense connection. connect directly to the junction of the external output filter capacitors. out senses the output voltage to determine the on-time for the high-side switching mosfet. out also serves as the feedback input in fixed-output modes. 7 4 ilim current-limit threshold adjustment. the current-limit threshold at cs is 0.1 times the voltage at ilim. connect ilim to a resistive divider (typically from ref) to set the current-limit threshold between 25mv and 300mv (with 0.25v to 3v at ilim). connect to v cc to assert the 100mv default current-limit threshold. 8 5 ref 2v reference voltage output. bypass to gnd with a 0.22? (min) bypass capacitor. can supply 50? for external loads. reference turns off in shutdown. 9 6 uvp undervoltage protection control input. an undervoltage fault occurs if the internal or external feedback voltage is less than the voltage at uvp. apply a voltage between 0.4v and 1v to set the undervoltage limit between 40% and 100% of the nominal output voltage. connect to v cc to assert the default undervoltage limit of 70% of the nominal output voltage. connect uvp to gnd or latch to v cc to disable undervoltage fault detection and clear the undervoltage protection latch. 10 7 pgood power-good, open-drain output. pgood is low when the output voltage is more than 10% above or below the normal regulation point or during soft-start. pgood is high impedance when the output is in regulation and the soft-start circuit has terminated. pgood is low in shutdown. 11 8 gnd analog and power ground 12 9 dl synchronous rectifier gate-driver output. swings from gnd to v dd . 13 10 v dd supply input for the dl gate drive. connect to the system supply voltage, 4.5v to 5.5v. bypass to gnd with a 1? (min) ceramic capacitor. pin description
standard application circuit the standard application circuit (figure 1) generates a 2.5v rail for general-purpose use in a notebook computer. see table 1 for component selections. table 2 lists com- ponent manufacturers. MAX8764 high-speed, step-down controller with accurate current limit for notebook computers _______________________________________________________________________________________ 9 pin qsop thin qfn name function 14 11 v cc analog supply input. connect to the system supply voltage, 4.5v to 5.5v, with a series 20 ? resistor. bypass to gnd with a 1? (min) ceramic capacitor. 15 12 ton on-time selection-control input. this four-level logic input sets the nominal dh on-time. connect to gnd, ref, v cc , or leave ton unconnected to select the following nominal switching frequencies: gnd = 600khz, ref = 450khz, floating = 300khz, and v cc = 200khz. 16 13 v+ battery-voltage sense connection. connect to input power source. v+ is used only to set the pwm one-shot timing. 17 14 skip pulse-skipping control input. connect to v cc for low-noise, forced-pwm mode. connect to gnd to enable pulse-skipping operation. 18 15 bst boost flying-capacitor connection. connect to an external capacitor and diode according to the standard application circuit (figure 1). see the mosfet gate drivers (dh, dl) section. 19 16 lx external inductor connection. connect lx to the switched side of the inductor. lx serves as the lower supply rail for the dh high-side gate driver. 20 17 dh high-side gate-driver output. swings from lx to bst. pin description (continued) table 1. component selection for standard applications component 2.5v at 4a c1 input capacitor 10?, 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m c2 output capacitor 330?, 6v kemet t510x477108m006as or sanyo 6tpb330m d1 schottky nihon ep10qy03 l1 inductor 4.7? coilcraft do33116p-682 or sumida cdrh124-4r7mc q1 high-side mosfet fairchild semiconductor 1/2 fds6982a q2 low-side mosfet fairchild semiconductor 1/2 fds6982a r sense 0.015 ? 1%, 0.5w resistor irc lr2010-01-r015f or dale wsl-2010-r015f table 2. component suppliers *distributor supplier usa phone factory fax coilcraft 847-639-6400 1-847-639-1469 dale-vishay 203-452-5664 1-203-452-5670 fairchild 408-822-2181 1-408-721-1635 irc 800-752-8708 1-828-264-7204 kemet 408-986-0424 1-408-986-1442 niec (nihon) 805-867-2555* 81-3-3494-7414 sanyo 619-661-6835 81-7-2070-1174 sumida 847-956-0666 81-3-3607-5144 taiyo yuden 408-573-4150 1-408-573-4159 tdk 847-390-4461 1-847-390-4405
detailed description the MAX8764 buck controller is targeted for low-voltage power supplies for notebook computers. maxim? propri- etary quick-pwm pulse-width modulator in the MAX8764 is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-transient timing problems of fixed-frequency, current-mode pwms while also avoiding the problems caused by widely varying switching frequencies in con- ventional constant-on-time and constant-off-time pwm schemes. 5v bias supply (v cc and v dd ) the MAX8764 requires an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebook? 95% efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear reg- ulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an exter- nal linear regulator such as the max1615. the battery and 5v bias inputs can be connected together if the input source is a fixed 4.5v to 5.5v supply. if the 5v bias supply is powered up prior to the MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 10 ______________________________________________________________________________________ v cc uvp v in 7v to 20v 5v bias supply c2 330 f see table 1 for other component selections. power-good indicator l1 4.7 h v out 2.5v shdn v+ d2 cmpsh-3 c6 3.3 f c7 0.1 f c4 0.22 f 270k ? 130k ? q1 d1 r2 100k ? q2 r sense 15m ? c5 4.7 f r1 20 ? skip ilim on/off control low-noise control dl lx bst dh cs out fb latch ovp pgood v dd MAX8764 5v ton ref gnd c1 10 f figure 1. standard application circuit
battery supply, the enable signal ( shdn ) must be delayed until the battery voltage is present to ensure startup. the 5v bias supply provides v cc and gate-drive power, so the maximum current drawn is: i bias = i cc + f (q g1 + q g2 ) = 5ma to 30ma (typ) where i cc is 550? (typ), f is the switching frequency, and q g1 and q g2 are the mosfet data sheet total gate-charge specification limits at v gs = 5v. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed-fre- quency, constant-on-time, on-demand pwm with voltage feed-forward (figure 2). this architecture relies on the out- put filter capacitor? esr to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp sig- nal. the control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ______________________________________________________________________________________ 11 figure 2. MAX8764 functional diagram ref -10% from out ref fb error amp toff ton ref +10% feedback mux (see figure 6) chip supply x2 1.0v r 0.1v por ovp 9r ilim v cc - 1v v cc - 1v v cc - 1v shdn pgood on-time compute ton 1-shot 1-shot trig in 2v to 28v trig q q s r 2v ref ref 5v output dl cs gnd v cc v dd lx zero crossing current limit dh bst 5v +5v q skip ton latch v+ MAX8764 s r q 0.7v 1.14v uvp 20ms timer ovp/uvp latch 0.1v out
MAX8764 width is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off-time (400ns typ). the on-time, one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the mini- mum off-time, one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the v+ input, and proportional to the output voltage. this algorithm results in a nearly constant switching frequency despite the lack of a fixed- frequency clock generator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output volt- age ripple. the on-time is given by: on-time = k (v out + 0.075v) / v in where k (switching period) is set by the ton pin-strap connection (table 4), and 0.075v is an approximation to accommodate for the expected drop across the low-side mosfet switch. one-shot timing error increases for the shorter on-time settings due to fixed propagation delays; it is approximately ?2.5% at 600khz and 450khz, and ?0% at the two slower settings. this translates to reduced switching-frequency accuracy at higher frequen- cies (table 5). switching frequency increases as a func- tion of load current due to the increasing drop across the low-side mosfet, which causes a faster inductor-current discharge ramp. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high-side power mosfet. two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and pc board resistance) and the dead-time effect. these effects are the largest contribu- tors to the change of frequency with changing load cur- rent. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times are added to the effective on-time. it occurs only in pwm mode ( skip = high) when the induc- tor current reverses at light or negative load currents. with reversed inductor current, the inductor? emf caus- es lx to go high earlier than normal, extending the on- time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is: f vv t(v v ) out drop1 on in drop2 = + + high-speed, step-down controller with accurate current limit for notebook computers 12 ______________________________________________________________________________________ table 3. operating mode truth table good operating point for compound buck designs or desktop circuits. +5v input 600 ton = gnd 450 ton = ref 3-cell li+ notebook useful in 3-cell systems for lighter loads than the cpu core or where size is key. considered mainstream by current standards. 4-cell li+ notebook 300 ton = floating 200 ton = v cc 4-cell li+ notebook use for absolute best efficiency. comments typical application frequency (khz) table 4. frequency selection guidelines shdn skip dl mode comments 0 x low shutdown, output uvp fault, thermal shutdown, uvlo low-power shutdown state. dl is forced to gnd. i cc < 1? typ. 1v cc switching run (pwm), low noise low-noise operation with no automatic switchover. fixed-frequency pwm action is forced regardless of load. inductor current reverses at light-load levels. low noise. high i q . 1 gnd switching run (pfm/pwm) normal operation with automatic pwm/pfm switchover for pulse skipping at light loads. best light-load efficiency. 1 x high fault fault latch has been set by overvoltage protection. device remains in fault mode until v cc power is cycled.
where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, and t on is the on-time calculated by the MAX8764. automatic pulse-skipping switchover in skip mode ( skip low), an inherent automatic switchover to pfm takes place at light loads (table 3). this switchover is affected by a comparator that trun- cates the low-side switch on-time at the inductor current? zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continu- ous and discontinuous inductor-current operation (also known as the ?ritical conduction?point; see the continuous-to-discontinuous inductor current vs. input voltage graph in the typical operating characteristics ). in low-duty-cycle applications, this threshold is relatively constant, with only a minor dependence on battery voltage. where k is the on-time scale factor (table 5). the load- current level at which pfm/pwm crossover occurs, i load( skip ) , is equal to 1/2 the peak-to-peak ripple cur- rent, which is a function of the inductor value (figure 3). for example, in the standard application circuit with k = 3.3? (table 5), v out = 2.5v, v in = 15v, and l = 6.8?, switchover to pulse-skipping operation occurs at i load = 0.51a or about 1/8 full load. the crossover point occurs at an even lower value if a swinging (soft-satura- tion) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low-input voltage levels). dc output accuracy specifications refer to the threshold of the error comparator. when the inductor is in continu- ous conduction, the output voltage has a dc regulation level higher than the trip level by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. forced-pwm mode ( skip = high) the low-noise, forced-pwm mode ( skip = high) disables the zero-crossing comparator, which controls the low- side switch on-time. this causes the low-side gate-drive waveform to become the complement of the high-side gate-drive waveform. this in turn causes the inductor current to reverse at light loads while dh maintains a duty factor of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be 10ma to 40ma, depending on the external mosfets. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, pro- viding sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple -output applications that use a flyback trans- former or coupled inductor. i kv 2l v-v v load(skip) out in out in ? MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ______________________________________________________________________________________ 13 figure 3. pulse-skipping/discontinuous crossover point inductor current i load = i peak / 2 on-time 0 time i peak l v batt -v out ? i ? t = figure 4. valley current-limit threshold point i limit i load 0 time i peak inductor current
MAX8764 current-limit circuit (ilim) the current-limit circuit employs a unique ?alley?cur- rent-sensing algorithm (figure 4). if the magnitude of the current-sense voltage at cs is above the current-limit threshold, the pwm is not allowed to initiate a new cycle. the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple cur- rent. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and battery voltage. there is also a negative current limit that prevents exces- sive reverse inductor currents when v out is sinking cur- rent. the negative current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with an external resistor-divider at ilim. a 1? (min) divider current is recommended. the current-limit threshold adjustment range is from 25mv to 300mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10 the voltage seen at ilim. the threshold defaults to 100mv when ilim is connected to v cc . the logic threshold for switchover to the 100mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signal seen by cs. mount or place the ic close to the low-side mosfet and sense resistor with short, direct traces, making a kelvin sense connection to the sense resistor. in figure 1, the schottky diode (d1) provides a current path parallel to the q2/r sense current path. accurate current sensing demands d1 to be off while q2 con- ducts. avoid large current-sense voltages that, com- bined with the voltages across q2, would allow d1 to conduct. if very large sense voltages are used, connect d1 in parallel with q2. mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving moder- ate-sized high-side, and larger low-side power mosfets. this is consistent with the low duty factor seen in the notebook environment, where a large v batt - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high-side fet from turning on until dl is fully off. there must be a low- resistance, low-inductance path from the dl driver to the mosfet gate for the adaptive dead-time circuit to work properly; otherwise, the sense circuitry in the MAX8764 interprets the mosfet gate as ?ff?while there is actual- ly still charge left on the gate. use very short, wide traces measuring no more than 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the MAX8764). the dead time at the other edge (dh turning off) is deter- mined by a fixed 35ns (typ) internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.5 ? (typ) on-resistance. this helps pre- vent dl from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfet. however, for high-current applications, there are still some combinations of high- and low-side fets that will cause excessive gate-drain coupling, which can lead to efficiency-killing, emi-producing, shoot-through currents. this is often remedied by adding a resistor in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 5). por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and soft-start counter, and preparing the pwm for operation. until v cc reaches 4.2v, v cc undervoltage lockout (uvlo) circuitry inhibits switching. dl is held low. when v cc rises above 4.2v, an internal digital soft-start timer begins to ramp up the maximum allowed current limit. the ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%; 100% cur- rent is available after 1.7ms ?0%. high-speed, step-down controller with accurate current limit for notebook computers 14 ______________________________________________________________________________________ bst +5v v in 5 ? dh lx MAX8764 figure 5. reducing the switching-node rise time
power-good output (pgood) the pgood window comparator continuously monitors the output. pgood is actively held low in shutdown, standby, and soft-start. after digital soft-start terminates, pgood is released if the output is within 10% of the nominal output voltage setting. note that the pgood window detector is completely independent of the over- voltage and undervoltage protection fault detectors. output overvoltage protection ovp controls the output overvoltage protection func- tion. connect ovp to v cc or latch to v cc to disable overvoltage protection. if overvoltage protection is enabled (ovp < 1.8v, latch = gnd), the output is continuously monitored. if the output exceeds the over- voltage protection threshold, overvoltage protection is triggered and the dl low-side gate-driver output is forced high. this turns on the low-side mosfet switch to rapidly discharge the output capacitor and reduce the output voltage. if latch is high, the overvoltage protection is dis- abled. if latch is low, the dl gate-driver output remains high until ovp is driven to v cc , or v cc is cycled below 1v. when the condition that caused the overvoltage persists (such as a shorted high-side mos- fet), the battery fuse opens. note that forcing dl high causes the output voltage to go slightly negative when energy has been previously stored in the lc tank circuit (see the output overvoltage waveforms in the typical operating characteristics ). if the load cannot tolerate being forced to a negative volt- age, it may be desirable to place a power schottky diode across the output to act as a reverse-polarity clamp. output undervoltage protection uvp controls the output undervoltage protection func- tion. connect uvp to gnd or latch to v cc to disable undervoltage protection. the output undervoltage pro- tection function is similar to foldback current limiting but employs a timer and latch rather than a variable current limit. if the output voltage is below the undervoltage pro- tection threshold after the output undervoltage protection blanking time has elapsed, the pwm is latched off, dl is pulled low, and the controller does not restart until v cc power is cycled. shdn is toggled, or uvp is pulled below 0.4v. connect uvp to v cc to enable the default undervoltage trip threshold of 70% of nominal. to select a different threshold, drive uvp to a voltage between 0.4v and 1v for a threshold between 40% and 100% of nominal. fixed-output voltages the MAX8764? dual mode operation allows the selec- tion of common voltages without requiring external com- ponents (figure 6). connect fb to gnd for a fixed 2.5v output or to v cc for a 1.8v output, or connect fb directly to out for a fixed 1v output. setting v out with a resistor-divider the output voltage can be adjusted from 1v to 5.5v with a resistor-divider if desired (figure 7). the equation for adjusting the output voltage is: where v fb is 1v. design procedure component selection for the MAX8764 is primarily dictat- ed by the following four criteria: 1) input voltage range . the maximum value (v in(max) ) must accommodate the worst-case high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to con- nectors, fuses, and battery selector switches. lower input voltages result in better efficiency. v v1 r1 r2 out fb =+ ? ? ? ? ? ? MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ______________________________________________________________________________________ 15 0.2v 2v out fb fixed 1.8v to error amp fixed 2.5v MAX8764 figure 6. feedback mux
MAX8764 2) maximum load current . there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus dri- ves the selection of input capacitors, mosfets, and other critical heat-contributing components. 3) switching frequency . this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the optimum fre- quency is also a moving target, due to rapid improve- ments in mosfet technology that are making higher frequencies more practical (table 4). 4) inductor operating point . this choice provides trade-offs between size vs. efficiency. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output rip- ple. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor val- ues lower than this grant no further size-reduction benefit. the MAX8764? pulse-skipping algorithm initiates skip mode at the critical conduction point. so, the inductor operating point also determines the load-current value at which pfm/pwm switchover occurs. these four factors impact the component selection process. selecting components and calculating their effect on the MAX8764? operation is best done with a spreadsheet. using the formulas provided, calculate the lir (the ratio of the inductor ripple current to the designed maximum load current) for both the minimum and maximum input voltages. maintaining an lir within a 20% to 50% range is recommended. the use of a spreadsheet allows quick evaluation of component selection. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: example: i load(max) = 8a, v in = 7v, v out = 1.5v, f = 300khz, 33% ripple current or lir = 0.33: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak induc- tor current (i peak ): i peak = i load(max) + [(lir / 2) ? i load(max) ] most inductor manufacturers provide inductors in stan- dard values, such as 1.0?, 1.5?, 2.2?, 3.3?, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load induc- tance decreases linearly with increasing current), evalu- ate the lir with properly scaled inductance values. transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maxi- mum duty factor, which can be calculated from the on- time and minimum off-time: l 1.5v (7v -1.5v) 7v 300khz 0.33 8a 1.49 h = = l = v(v- v) v f lir i out in out in load(max) high-speed, step-down controller with accurate current limit for notebook computers 16 ______________________________________________________________________________________ dl gnd out cs dh fb v batt v out r1 r2 MAX8764 figure 7. setting v out with a resistor-divider
where and minimum off-time = 400ns (typ) (see table 5 for k values). the amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: setting the current limit for most applications, set the MAX8764 current limit by the following procedure: 1) determine the minimum (valley) inductor current i l(min) under conditions when v in is small, v out is large, and load current is maximum. the minimum inductor current is i load minus half the ripple cur- rent (figure 4). 2) the sense resistor determines the achievable current-limit accuracy. there is a trade-off between current-limit accuracy and sense-resistor power dis- sipation. most applications employ a current-sense voltage of 50mv to 100mv. choose a sense resistor so that: r sense = cs threshold voltage / i l(min) extremely cost-sensitive applications that do not require high-accuracy current sensing can use the on- resistance of the low-side mosfet switch in place of the sense resistor by connecting cs to lx (figure 8b). use the worst-case value for r ds(on) from the mosfet q2 data sheet, and add a margin of 0.5%/? for the rise in r ds(on) with temperature. then use that r ds(on) value and i l(min) from step 1 above to deter- mine the cs threshold voltage. if the default 100mv threshold is unacceptable, set the value as in step 2 above. in all cases, ensure an acceptable cs threshold volt- age despite inaccuracies in resistor values. output capacitor selection the output filter capacitor must have low enough effective series resistance (esr) to meet output ripple and load- transient requirements, yet have high enough esr to sat- isfy stability requirements. for cpu core voltage converters and other applications where the output is subject to violent load transients, the output capacitor? size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capaci- tance: in noncpu applications, the output capacitor? size often depends on how much esr is needed to maintain an acceptable level of output voltage ripple: the actual microfarad capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tantalums, os-cons, and other electrolytics). when using low-capacity filter capacitors, such as ceramic or polymer types, capacitor size is usually deter- mined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (also, see the v sag and v soar equation in the transient response section). r v lir i esr p-p load(max) r v i esr dip load(max) l v f x lir x i out load max = () duty k (v + 0.075v)/ v k (v + 0.075v)/ v + min off - time out in out out = v (i ) l 2 c duty (v - v ) sag load(max) 2 out in(min) out = ? MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ______________________________________________________________________________________ 17 dl cs lx a) b) MAX8764 dl cs lx MAX8764 figure 8. current-sense circuits
MAX8764 output capacitor stability considerations stability is determined by the value of the esr zero rela- tive to the switching frequency. the point of instability is given by the following equation: where: for a typical 300khz application, the esr zero frequency must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero frequencies of 25khz. in the design example used for inductor selec- tion, the esr needed to support 60mv p-p ripple is 60mv/2.7a = 22m ? . two 470?/4v kemet t510 low-esr tantalum capacitors in parallel provide 22m ? (max) esr. their typical combined esr results in a zero at 27khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. large ceramic capacitors can have a high esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but dis- tinctly different ways: double-pulsing and fast-feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough volt- age ramp in the output voltage signal. this ?ools?the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt- age protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to monitor simultaneously the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under- or overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. nontantalum chemistries (ceramic, aluminum, or os- con) are preferred due to their resistance to power-up surge currents: for optimal circuit reliability, choose a capacitor that has less than 10? temperature rise at the peak ripple current. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>5a) when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. for maximum efficiency, choose a high-side mosfet (q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15v). check to ensure that the conduction losses at minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget. check to ensure that conduction losses plus switching losses at the maxi- mum input voltage do not exceed the package ratings or violate the overall thermal budget. choose a low-side mosfet (q2) that has the lowest possible r ds(on) , comes in a moderate to small pack- age (i.e., 8-pin so), and is reasonably priced. ensure that the MAX8764 dl gate driver can drive q2; in other words, check that the gate is not pulled up by the high- side switch turn on, due to parasitic drain-to-gate capac- itance, causing crossconduction problems. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the buck topology. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case power dissipation due to resistance occurs at minimum battery voltage: pd(q1 resistive) = (v out / v in(min) ) ? i load 2 ? r ds(on) generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- i i vv-v v rms load out in out in = () ? ? ? ? ? ? ? ? ? ? f f f 1 2r c esr esr esr out = = high-speed, step-down controller with accurate current limit for notebook computers 18 ______________________________________________________________________________________
pation limits often limits how small the mosfet can be. again, the optimum occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. high-side switching losses do not usually become an issue until the input is greater than approximately 15v. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f switching loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , reconsider the choice of mosfet. calculating the power dissipation in q1 due to switching losses is difficult, since it must allow for difficult-to-quanti- fy factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a sanity check using a thermocouple mounted on q1: where c rss is the reverse transfer capacitance of q1, and i gate is the peak gate-drive source/sink current (1a typ). for the low-side mosfet, q2, the worst-case power dis- sipation always occurs at maximum battery voltage: pd(q2) = (1 - v out / v in(max) ) ? i load 2 ? r ds(on) the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit. to protect against this possibility, you must ?verdesign?the circuit to tolerate i load = i limit(high) + [(lir / 2) ? i load(max) ], where i limit(high) is the maxi- mum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance vari- ation. if short-circuit protection without overload protec- tion is adequate, enable undervoltage protection, and use i load(max ) to calculate component stresses. choose a schottky diode d1 having a forward voltage drop low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional, and if efficiency is not critical it can be removed. applications information dropout performance the output voltage adjust range for continuous-conduc- tion operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. for best dropout per- formance, use the slower ( 200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k- factor. this error is greater at higher frequencies (table 5). also, keep in mind that transient response perfor- mance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the transient response section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down indicates the circuit? ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle, and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but this can be adjusted up or down to allow trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths, t off(min) is from the electrical characteristics table, and k is taken from table 5. the absolute minimum input voltage is cal- culated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipat- ed, calculate v sag to be sure of adequate transient response. v vv th k vv in min out drop off min drop drop () () = + () ? ? ? ? ? ? ? ? + 1 21 1- - pd(q1 switching) cv fi i rss in(max) 2 load gate = MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ______________________________________________________________________________________ 19
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 20 ______________________________________________________________________________________ dropout design example: v out = 2.5v fsw = 300khz k = 1.8?, worst-case k = 2.97? t off(min) = 500ns v drop1 = v drop2 = 100mv h = 1.5: calculating again with h = 1 gives the absolute limit of dropout: v vv s s vv v in min () .. . . . . . = + () ? ? ? ? ? ? ? += 25 01 1 05 1 297 01 01 313 - - v vv s s vv v in min () .. . . . .. . = + () ? ? ? ? ? ? ? += 25 01 1 05 15 297 01 01 348 - - agnd plane pgnd plane via to ic out power ground via to ic cs pin v dd bypass ref bypass v cc bypass use agnd plane to: - bypass v cc and ref - terminate external fb, ilim, ovp, uvp dividers - pin-strap control inputs use pgnd plane to: - bypass v dd - connect ic gnd pin to top-side power ground via to power ground top side bottom side v out l1 c1 c2 d1 q1 v in q2 q via r s via to pgnd plane and ic gnd pin figure 9. power-stage pc board layout example table 5. approximate k-factor errors ton setting (khz) approximate k-factor error (%) minimum v in at v out = 2v (v) 200 ?0 2.6 300 ?0 2.9 450 ?2.5 3.2 600 ?2.5 3.6 k factor (s) 5 3.3 2.2 1.7
therefore, v in must be greater than 3.13v, even with very large output capacitance, and a practical input volt- age with reasonable output capacitance would be 3.48v. pc board layout guidelines careful pc board layout is critical to achieving low switching losses and clean, stable operation. the switch- ing power stage requires particular attention (figure 9). if possible, mount all power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pc board lay- out: keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. minimize current-sensing errors by connecting cs directly to the r sense terminal. when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst, lx, dh, and dl) away from sensitive analog areas (ref, fb, cs). layout procedure 1) place the power components first, with ground termi- nals adjacent (q2 source, c in- , c out- , d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to mosfet q2, preferably on the back side opposite q2 to keep lx, gnd, and the dl gate-drive lines short and wide. the dl gate trace must be short and wide, measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1in from the controller ic gnd pin. 3) group the gate-drive components (bst diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figure 9 . this diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an ana- log ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. MAX8764 high-speed, step-down controller with accurate current limit for notebook computers ______________________________________________________________________________________ 21 chip information transistor count: 2963 process: bicmos pin configurations 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 dh lx bst skip ovp shdn latch cs top view v+ ton v cc v dd ref ilim out fb 12 11 9 10 dl gnd pgood uvp MAX8764eep qsop 3 2 1 20 19 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 thin qfn MAX8764etp v cc ton v+ skip bst ref ilim out fb ovp lx dh cs latch shdn v dd dl gnd pgood uvp + +
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers 22 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps
MAX8764 high-speed, step-down controller with accurate current limit for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 23 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e xxxxx marking h 1 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- l e/2 common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3, and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 yes 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 no 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 yes 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. h 2 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. 3.30 t4055-1 3.20 3.40 3.20 3.30 3.40 ** yes 0.05 00.02 0.60 0.40 0.50 10 ----- 0.30 40 10 0.40 0.50 5.10 4.90 5.00 0.25 0.35 0.45 0.40 bsc. 0.15 4.90 0.25 0.20 5.00 5.10 0.20 ref. 0.70 min. 0.75 0.80 nom. 40l 5x5 max. 13. lead centerlines to be at true position as defined by basic dimension "e", 0.05.

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